Editor’s note: This
article is by IBM Research scientists Jeehwan Kim and Hongsik Park, who work in carbon electronics.
|Dr. Jeehwan Kim|
holds promise as the linchpin material for breakthroughs in everything from high-frequency
transistors and photo-detectors, to flexible electronics and biosensors because
of its supreme electrical, optical and mechanical properties
while some labs, IBM included, have been able to demonstrate its abilities in high-speed transistors,
the performance is still limited by the quality and size of graphene. The extremely
high fabrication cost for high-quality graphene is also another hurdle for many
of these potential applications.
Our team at IBM’s Thomas J. Watson Research
Center is getting close
to making this feasible, as we are the first to successfully develop a
reproducible technique to fabricate single-oriented, single-layer graphene at wafer-scale.
|Dr. Hongsik Park|
Two-dimensional semiconductor materials need to be a perfect single layer so
their unique properties can be harnessed. In our paper “Layer-Resolved Graphene
Transfer via Engineered Strain Layers” – published in Science this month – we used the idea that every element in the
periodic table has a different adhesion (atomic binding energy) to graphene in
order to produce single-oriented, single-layered graphene at a wafer-scale.
From sub-millimeter flakes to 4-inch wafers
For high performance device application, graphene – which
looks like a 2D honeycomb of crystalline carbon atoms – must have uniform orientation and thickness.
So, the atoms in a sheet of graphene must be aligned and “smoothed” to a single
The realization of large scale oriented graphene has
been a hot research topic for more than a decade. But since the first
demonstrations of removing graphene from graphite, by using the so-called “scotch
tape method” of peeling away the graphene, the size of single-oriented graphene
has been limited to less than a square millimeter – too small for real world use. Our new techniques, though, show how it’s
possible to break through this decade-old barrier and make 100 millimeter diameter wafer-scale sheets of graphene (4 inches).
To do this, we exfoliate the graphene twice. The first exfoliation
separates graphene from a silicon carbide (SiC) substrate by usinga stressed
nickel layer. Once this step is completed, we perform a
second exfoliation that removes any graphene in excess of a single-layer by using a thin gold layer – thus leaving only
single-layer, single-oriented graphene.
IBM Research’s earlier work on a graphene transistor
did produce the world’s
fastest graphene transistor (reaching 100 GHz) by using graphene formed on
SiC. But the graphene was restricted to an expensive SiC substrate in the lab
previously, unable to be cost-effectively mass produced.
Our technique sets the graphene free.
Just being able to reproduce the separation of graphene
from one SiC wafer over and over again will immediately lower the cost,
as the graphene won’t depend on the SiC substrate for use in transistors. Also, the
active graphene device area, when on SiC, is restricted to just a few
micrometers because multiple layers of graphene impede performance. Now, we can
“grow” single-layer graphene to much larger, usable, sizes.
According to Nature’s 2012 “Graphene
Roadmap,” current transistor performance will top off in the year 2021, but the
progress of graphene in the next generation of transistors could not only pick
up where silicon will leave off, it could deliver up to 1 THz of high-speed compute
operation over the next decade.
Labels: graphene, ibmresearch, silicon, transistor