note: This article is by IBM Research Scientist Dr. Sani Nassif.
University of Glasgow and the Scottish Funding Council are collaborating on a
project to simulate 3D microprocessor transistors at a mere 14 nanometer scale
(the virus that causes the common cold is more than twice as large at 32 nanometers). Using a silicon-on-insulator
(SOI) substrate, the FinFET (fin field-effect transistor) project, called StatDES,
promises to keep improving microprocessor performance and energy conservation.
from flat to 3D transistors
in everything from mainframes to phones are almost all built with planar complimentary metal-oxide-semiconductor field-effect transistors – CMOS FETs. A
design that goes back to the late 1950s, these transistors sit next to one
another on the chip. It's a design that is falling out of favor as we work
towards more powerful, more efficient devices that don't take up more energy to
transistor’s raised pillar of silicon (the “fin”) is the conduit for current flow, and is modulated
by a gate that surrounds the fin. The gate acts much like how stepping on a garden
hose stops the water from flowing.
In flat devices, this modulation comes from one side only (the top),
while FinFETs allow this modulation from two sides, and therefore allow the
flow to be turned off much more effectively. This increased effectiveness
translates to improved performance and reduced wasted energy.
the industry is quickly catching on to FinFETs. The design is 37 percent faster
in low-voltage applications and uses 50 percent less power than CMOS FETs.
the challenge to scale FinFET technology
The StatDES project is tweaking the FinFET design to improve its
scalability. Up until now, they have been made by etching grooves in a bulk
wafer, so extra steps are required to ensure that each FinFET is insulated from
the others. IBM avoids the issues of etching grooves in the wafer by putting the
transistors on an insulating Silicon-Oxide using standard SOI.
shape affects current flow in the same way that the shape of that garden hose
affects the amount of water flowing through it.
University of Glasgow Professor and GSS CEO Asen Asenov writes
that as more current is conducted through the device, it crowds into the apex
of the triangle. As a result, the triangular shape fins result in a 12 – 15
percent performance reduction compare to rectangular shape fins.
told the EE
Times that “moving to FinFETs constructed on SOI wafers could solve
a number of problems ... The buried oxide layer means you don't have the
problem of filling trenches.”
easier-to-fabricate SOI FinFETs with rectangular fins can deliver 20 – 25
percent improvement in performance compared to the current mass production bulk
StatDES project is set to simulate 14 nm SOI FinFETs, and make predictions that
will help designers determine how they will get the maximum utilization of this
FinFET on SOI means for IT
When FinFETs become widely available, the industry can expect the
continuation of the historical trends of technology performance, over time –
Moore’s Law. Today’s planar devices will not be able to follow this trend.
Without moving to FinFETs, we would be stuck with the computers and devices we
Labels: Asen Asenov, austin, CMOS, finFET, silicon, SOI, transistor